1. Field of the Invention
The present invention relates to a dielectrically separated wafer and a fabrication method for the same, and particularly relates to a dielectrically separated wafer provided with dielectrically separated silicon islands having a N on N+ or a P on P+ structure with different dopants at different depths, to suppressing the growth of voids (gaps) when the polysilicon layer is grown on the surface of a dielectrically separating oxide film, and to flattening the surface between one dielectrically separated silicon island and another dielectrically separated island.
2. Description of the Related Art
A laminated dielectrically separated wafer is known as one type of laminated silicon wafer. The conventional laminated dielectrically separated wafer is fabricated by each of the processes shown in FIG. 15. FIG. 15 shows the cross-sectional structure of the dielectrically separated wafer fabricated by this method.
First, a silicon wafer is prepared whose active layer surface is mirror polished (FIG. 15(a)). Either an N-type or a P-type can be used. Next, a mask oxide film 11 is formed on the surface of this silicon wafer (FIG. 15(b)). Furthermore, a photoresist 12 is attached to the oxide film, and by photolithography windows are formed at specified locations. Additionally, the oxide film 11 exposed in these windows is eliminated, and windows having a specified pattern are formed on the oxide film. As a result, one part of the surface of the silicon wafer 10 is exposed. Next, after removing the photoresist 12, this silicon wafer 10 is immersed in an alkaline etchant, and the surface of the wafer. undergoes anisotropic etching (FIG. 15(c)).
In this manner, dielectrically separating grooves 13 having a v-shaped cross-section are formed on the wafer surface.
Moreover, in this context, anisotropic etching is etching whose etching speed in the vertical direction is larger than the horizontal direction, and thus is directionally dependent due to the crystalline orientation of the silicon wafer 10.
Next, the mask oxide film 11 is cleaned and removed using a dilute HF solution (dilute hydrofluoride solution) or a buffer hydrofluoride solution (FIG. 15(d)). Subsequently, the dielectrically separating oxide film 14 of a specified thickness is formed on the silicon wafer surface, including the dielectrically separating grooves 13.
Next, the surface of this silicon wafer 10, that is, on the dielectrically separated oxide surface 14, a high temperature polysilicon layer 16 is grown to a specified thickness by the high temperature CVD method, at approximately 1200xc2x0xcx9c1300xc2x0 C. (FIG. 15(f)). Next, the peripheral portion of the wafer is chamfered, and as necessary, the undersurface of the wafer is flattened. Next, the high temperature polysilicon layer 16 of the wafer surface is cut and polished to a thickness of approximately 10xcx9c80xcexc.
In addition, as necessary, subsequently a low temperature polysilicon layer 17 having a thickness of 1xcx9c5xcexc is formed on the wafer surface by the lower temperature CVD method at approximately 550xcx9c700xc2x0 C., and the surface of the low temperature polysilicon layer 17 is polished in order to produce a mirror surface on the laminated surface.
In contrast, a silicon wafer 20 that serves as the support substrate wafer is prepared separately (FIG. 15(h)). The surface of this wafer is mirror polished. Next, the mirror surface of the silicon wafer 10 is brought into contact with and laminated on the mirror surface of the silicon wafer 20 (FIG. 15(i)).
Subsequently, a specified annealing is carried out in order to increase the lamination strength of these laminated wafers.
Next, as shown in FIG. 15(j), the peripheral portion of the active surface wafer of these laminated wafers is chamfered. In addition, the laminated wafer having the active surface is ground and polished. The amount of grinding of this active surface wafer exposes to the outside a part of the dielectrically separating oxide film 14, and on the surface of the high temperature polysilicon surface 16, dielectrically separated silicon islands 30 defined by the dielectrically separating oxide film 14 are realized.
Three problems are encountered in the conventional dielectrically separated wafers. The first problem is related to the restricted surface area for manufacturing the semiconductor device on the dielectric separated wafer; the second problem is related to a void (gap) B, which is an air bubble defect, will develop between the neighboring polysilicon cores; and the third problem is related to the surface steps caused by the differences of the grinding speed of the constituting layers. These three problems will be described hereinafter.
The first problem will be described. In recent years, the power IC for a large electric current has been developed. In the power IC, a dielectrically separated structure wherein each element is completely separated by a dielectrically separating oxide film has been adopted. In these elements, in order to sustain well the falling voltage of the PN junction, it is necessary to make the specific resistance of the dielectrically separated silicon islands very high.
However, a high specific resistance limits the voltage of the elements during operation, incurring the disadvantage of increasing what is termed the operational resistance.
Thus, generally, between the dielectrically separated silicon islands and the dielectrically separating oxide film a high concentration impurity layer (N+ region and P+ region) is provided in which impurities are diffused in high concentration. This high concentration impurity layer serves as the path for the current and reduces the increase in operational resistance.
In this type of dielectrically separated wafer, conventionally, as shown in FIG. 16, the high concentration impurity layer 30a is formed along the dielectrically separating oxide film 14 having a saucer shape, and on the inside of this high concentration impurity layer 30a a low concentration impurity layer 30b is defined.
In order to fabricate this dielectrically separated wafer, first the surface of a silicon wafer having a low concentration of impurities (dopants) undergoes anisotropic etching, and dielectrically separating grooves are formed. Subsequently, over the entire surface of the silicon wafer on which the dielectrically separating grooves have been formed, a high concentration impurity layer 30a is formed at a specified depth by thermally diffusing or ion implanting a dopant having the same conductivity. Subsequently, the dielectrically separating oxide film 14, etc., are formed, and further, as described above, by grinding and polishing the undersurface of the wafer, dielectrically separated silicon islands 30 having a N on N+ structure or a P on P+ structure are realized on the wafer surface.
However, because the high concentration impurity layer of the dielectrically separated wafer according to this type of conventional technology has a saucer shaped surface cross-section, like the dielectrically separating oxide film, the peripheral portion of the surface of the dielectrically separated silicon islands is structured by a high concentration impurity layer.
As a result, first problems arise that it is necessary to manufacture a device avoiding the regions of this exposed high concentration impurity layer, and the fabrication surface area of the device at the dielectrically separated silicon islands becomes small.
Next, the second problem will be described. As described before, the conventional laminated dielectrically separated wafer is fabricated by each of the processes shown in FIG. 15. However, according to the conventional fabrication method of the dielectrically separated wafer, during the growth period of the polysilicon layer 16 by the high temperature CVD method, as shown in FIG. 15, in the case that there exists a particle P, a defect, etc., on the surface of the dielectrically separating oxide film 14, the polysilicon slowly develops these as growth nuclei.
As a result, among the groups many groups of polysilicon cores 16 a that grow the particles, etc., as growth nuclei, there is the concern that a void (gap) B, which is an air bubble defect, will develop between the neighboring polysilicon core 16a and polysilicon core 16a. 
Therefore, as subsequent steps are completed, in the case that this void B is exposed on the surface of the dielectrically separated wafer, this part becomes a concavity, and there is the inconvenience that contaminants will remain therein. In addition, even in the case that this void B is not exposed on the surface of the dielectrically separated wafer, there is the concern that in the device fabrication process on the user side, this void B might cause thermal deterioration of the dielectrically separated wafer.
The third problem will be described next. According to the above-described type of conventional dielectrically separated wafer fabrication method, in the finishing process of the laminated dielectrically separated wafer, the surface of the wafer 10 having the active layer is ground, and using an alkaline abrasive, this ground surface is polished until the dielectrically separated silicon islands 10A, which are insulated by a dielectrically separating oxide film 14, appear.
FIG. 12 is a drawing showing the relationship between the amount of polishing of the surface of the dielectrically separated wafer and the distance between neighboring dielectrically separated silicon islands. FIG. 13 is an enlarged cross-sectional diagram of the necessary components of the dielectrically separated wafer fabricated by minimizing the amount of polishing according to conventional means. FIG. 14 is an enlarged cross-sectional diagram of the necessary components of the dielectrically separated wafer fabricated by maximizing the amount of polishing according to conventional means.
In FIG. 12, D is the total depth (about 70 xcexcm) of dielectrically separating grooves, L1 is the amount of polishing of the dielectrically separating silicon island 10A, L2 is the amount remaining after polishing the dielectrically separated silicon island 10A, and W is the distance between one dielectrically separated silicon island 10A and another dielectrically separated silicon island 10A. The angle xcex8 of the side walls of the dielectrically separated grooves is 54.7xc2x0.
As shown in FIG. 14, because the bottom portion of the dielectrically insulating grooves 13 of the active surface wafer 10 are polished when the surface is polished, the larger the amount of polishing L1 becomes, the longer the distance W between the dielectrically separated islands 10A becomes. Contrarily, the smaller the amount of grinding L1, the shorter distance W becomes.
In this connection, when actually trying to polish the surface of the active layer wafer 10, it became apparent that the cross-sectional form of the surface of the high temperature polysilicon layer 16 that is exposed between the dielectrically separated islands 10A varies.
That is, when the amount of polishing L1 is small, at about, for example, 10 xcexcm, the distance W became narrow, and its exposed portion, that is, along the V-shaped groove of the dielectrically separated oxide film 14, grew, and then at the border to the high temperature polysilicon layer 16, a projection 16b developed (refer to FIG. 13). In addition, when the amount of polishing L1 is increased to, for example, 25 xcexcm, the distance W becomes long, and an indentation 16a develops along this edge (refer to FIG. 14).
Generally, if the amount of polishing L1 is made decreased, it is preferable that the surface area of the dielectrically separated silicon islands 10A upon which devices can be manufactured be enlarged by that amount. However, on the one hand, making the amount of polishing L1 small produces projections 16b of approximately 0.3 xcexcm, which is the absolute value of the difference between the maximum value and the minimum value when measured by a stylus-profilometer. Consequently, for example, during the contact exposure of the device fabrication process, the mask (not shown in the figures) that covers the wafer surface can be damaged, and the resist in the vicinity of the projection 16b can easily remain. Thus, problems such as defective patterns, insufficient resolution, separation of the mask, etc., are easily incurred.
On the other hand, if the amount of polishing L1 is made large, on the surface of the active layer wafer 10, an indentation 16a is produced due to the difference in polishing speed of the various layers 10A, 14, and 16 that form this surface. In particular, at the above-mentioned border, compared to the dielectrically separated silicon islands 10A and the dielectrically separating oxide film 14, the speed of the progress of the etching becomes fast and produces indentations 16a of approximately 0.3 xcexcm, which is the absolute value of the difference between the maximum value and the minimum value when measuring with a stylus-profilometer.
If this type of deep steps are formed after shipping the product, when the user fabricates devices in the photolithography process, for example, this interferes with applying the resist uniformly to the wafer surface, and this incurs the problems of disconnected circuits and deterioration of resolution. Furthermore, when removing the resist film after exposure, a part of the film may remain on the surface of the wafer. In addition, in other processes as well, the indentation 16a becomes a site that absorbs contaminants. Furthermore, there is the problem that normally the contaminants absorbed by the indentation 16a cannot easily be eliminated because the width of the indentation 16a is narrow.
An object of the first embodiment of this invention is to solve the first problem by providing a dielectrically separated wafer that can expand the device fabrication area on the dielectrically separated silicon islands. The object of the first embodiment also includes to provide a fabrication method for a dielectrically separated wafer that can expand the device fabrication surface area.
In a first aspect of the first embodiment of the present invention, in a dielectrically separated wafer having a plurality of dielectrically separated silicon islands mutually defined by a dielectrically separating oxide film, these dielectrically separated silicon islands have a high concentration impurity layer formed at the bottom of the islands and a low concentration impurity layer having an identical conductivity laminated on the high concentration impurity layer.
In a method wherein dielectrically separated silicon islands have a N on N+ structure or a P on P+ structure, as shown in the second aspect of the first embodiment of the invention, a method is presented in which dopants of identical conductivity are given a differential concentration by thermal diffusion or ion implantation.
It is also possible that the dielectrically separated wafer be a laminated wafer wherein a support substrate wafer is laminated on the undersurface of a dielectrically separated wafer having a thinned polysilicon layer.
The thickness of the high concentration impurity layer is, for example, 1xcx9c10xcexc, but can be decided according to convenience depending on the device to be fabricated.
A second aspect of the first embodiment of the present invention is a dielectrically separated wafer fabrication method including a step of forming a high concentration impurity layer including at a high concentration impurities of identical conductivity at a specified depth range below the surface of the silicon wafer and a low concentration impurity layer including at low concentrations impurities of identical conductivity at a specified depth range from this high concentration impurity layer; a step of forming a dielectrically separating groove deeper than the above high concentration impurity layer on the surface of this silicon wafer; a step of forming a dielectrically separated oxide film on this dielectrically separating groove and on each surface of the of the silicon wafer; a step of laminating a polysilicon layer on this dielectrically separated oxide film; and a step of grinding and polishing the silicon wafer from the undersurface and realizing a plurality of dielectrically separated silicon islands separated by this dielectrically separating oxide film on this polished surface, and wherein this high concentration impurity layer is formed on the bottom of these dielectrically separated silicon islands and the low concentration impurity layer is formed on this high concentration impurity layer.
As a method for growing the polysilicon layer, it is possible to use the high temperature CVD method. In this method, a material gas including silicon is introduced into a reactive furnace along with a carrier gas (H2 gas, etc.), and precipitate silicon is grown by thermal decomposition or reduction of the atomic gas on the silicon wafer which has been heated to a high temperature. Normally, SiCl4, DiHCl3, etc., are used as compounds that include silicon.
In the reaction furnace, in a dome shaped quartz bell jar, there is also a pancake type furnace wherein the gas is introduced, and heated by high frequency induction while rotating a susceptor on which the silicone wafer is mounted. In addition to this, the silicon wafer is laminated to each surface of a six-sided columnar susceptor accommodated inside the quartz container, and subsequently, it is possible to use, for example, a cylinder (barrel) type furnace wherein this susceptor is rotated while being heated by gas introduced or an infrared lamp.
The temperature for growing the polysilicon differs depending on the heating method of the furnace. In the most widely used pancake furnace applied for this use, 1200xc2x0xcx9c1290xc2x0 C. is preferable, and 1230xc2x0xcx9c1280xc2x0 C. is more preferable. Below 1200xc2x0 C., the inconvenience in incurred that the silicon wafer is easily cracked, and above 1290xc2x0 C., the inconvenience is incurred that slips are produced, and the silicon wafer can become cracked.
For a thickness 2 or 3 times the thickness obtained by anisotropic etching, the thickness of the polysilicon layer is the thickness to which the thickness of the polysilicon layer to be left is added. At double or less the thickness of the polysilicon layer that is produced by anisotropic etching, the grooves made by anisotropic etching may not be sufficiently covered. On the other hand, at three times or greater, it may be unnecessarily thickly deposited.
For the anisotropic etchant, it is possible to use alkaline etchants such as KOH (IPA/KOH/H2O), KOH (KOHH2O), KOH (hydrazine/KOH/H2O). The normal conditions for anisotropic etching can be adopted.
In addition, it is possible to use generally adopted conditions for each step in forming the windows of the isotropic etching on the negative resist film on the surface of the wafer.
It is possible to use well-known methods of thermal diffusion that thermally diffuse dopants of a specified conductive type (N-type or P-type). That is, using a thermal diffusion furnace, while feeding gases such as PH3, Sb2O3, and BBr3, the furnace temperature is maintained in an appropriate range, 600xcx9c1250xc2x0 C.
Concretely, for example, an N-type dopant, such as phosphorus, or P-type dopant, such as boron, that have the same conductivity as the wafer, is thermally diffused over the surface of a silicon wafer that has incorporated a low concentration dopant over its entirety. Thereby, a lamination having an N on N+ structure or a P on P+ structure is formed within the region of the silicon island formations.
In addition, ion implantation can also be used. That is, using an ion implantation apparatus, the dopant (impurity) of the same conductivity is gasified and ionized, accelerated by an electrical field, and driven into the silicon wafer surface.
Dopant can be incorporated into the silicon wafer before forming the dielectrically separating grooves by anisotropic etching. For example, before the step of applying the mask oxide film (or a nitride film) to the silicon wafer.
Furthermore, the depth of the dielectrically separating grooves formed on the silicon wafer surface must be deeper than the high concentration impurity layer, and as deep as the low concentration impurity layer.
The object of the second embodiment of this invention is to provide a dielectrically separated, wafer that does not have exposed concavities in the polysilicon layer surface anal eliminates voids from the interface between the polysilicon layer and the dielectrically separating oxide layer.
In addition, another object of the second embodiment of this invention is to provide a fabrication method for a dielectrically separated wafer in which there is no development of voids at the interface between the dielectrically separating oxide film and the polysilicon layer.
A first aspect of the present invention is a dielectrically separated wafer having a polysilicon layer and a plurality of silicon islands mutually insulated by the dielectrically insulating oxide film formed on the surface of this polysilicon layer, and wherein this polysilicon layer has a seed polysilicon layer that is grown by a low temperature CVD method on the interface with the dielectrically insulating oxide film.
In addition to having a support substrate with a thickened polysilicon layer, the dielectrically separated wafer can have a supporting substrate laminated on the undersurface of the dielectrically separated wafer that has a thinned polysilicon layer.
A second aspect of the present invention is a fabrication method for a dielectrically separated wafer wherein dielectrically separating grooves are formed on the surface of the silicon wafer, a dielectrically separating oxide film is formed on the surface of the silicon wafer including the surface of these dielectrically separating grooves, a polysilicon layer is formed on the surface of this dielectrically separating oxide film, this polysilicon wafer is ground and polished from this underside, and a plurality of dielectrically separated silicon islands separated by the dielectrically separating oxide film on this polished surface are realized, and wherein a seed polysilicon layer is grown by low temperature the CVD method on the surface of this dielectrically separating oxide film, and subsequently a polysilicon layer is grown using the high temperature CVD method on the surface of this seed polysilicon layer.
As a method for growing the polysilicon layer, it is possible to use the high temperature CVD method. In this method, a material gas including silicon is introduced into a reactive furnace along with a carrier gas (H2 gas, etc.), and precipitate silicon is grown by thermal decomposition or reduction of the atomic gas on the silicon wafer which has been heated to a high temperature. Normally, SiCl4, DiHCl3, etc., are used as compounds that include silicon.
In the reaction furnace, in a dome shaped quartz bell jar, there is also a pancake type furnace wherein the gas is introduced, and heated by high frequency induction while rotating a susceptor on which the silicone wafer is mounted. In addition to this, the silicon wafer is laminated to each surface of a six-sided columnar susceptor accommodated inside the quartz container, and subsequently, it is possible to use, for example, a cylinder (barrel) type furnace wherein this susceptor is rotated while being heated by gas introduced or an infrared lamp.
The temperature for growing the polysilicon differs depending on the heating method of the furnace. In the most widely used pancake furnace applied for this use, 1200xc2x0xcx9c1290 C. is preferable, and 1230xc2x0xcx9c1280xc2x0 C. is more preferable. Below 1200xc2x0 C., the inconvenience in incurred that the silicon wafer is easily cracked, and above 1290xc2x0 C., the inconvenience is incurred that slips are produced, and the silicon wafer can become cracked.
For a thickness 2 or 3 times the thickness obtained by anisotropic etching, the thickness of the polysilicon layer is the thickness to which the thickness of the polysilicon layer to be left is added. At double or less the thickness of the polysilicon layer that is produced by anisotropic etching, the grooves made by anisotropic etching may not be sufficiently covered. On the other hand, at three times or greater, it may be unnecessarily thickly deposited.
As a method of growing the seed polysilicon layer, a low temperature CVD method at atmospheric pressure or reduced pressure is used. In this method, like the high temperature CVD method, a material gas including silicon is introduced into a reactive furnace along with a carrier gas (H2 gas, etc.), and precipitate silicon is grown by thermal decomposition or reduction of the atomic gas on the silicon wafer which has been heated to a high temperature. Normally, SiCl4, DiHCl3, etc., are used as the compounds that include silicon. In the reaction furnace, in a dome shaped quartz bell jar, there is also a pancake type furnace wherein the gas is introduced, and heated by high frequency induction while rotating a susceptor on which the silicone wafer is mounted. A horizontal reaction furnace resistance heated from the outside of the quartz bell jar or a vertical reaction furnace in which a quartz tube is laid horizontally, a boat in which the silicon wafer is laid is accommodated within the tube, and resistance heating is applied form outside the tube while the gas is introduced.
The growth temperature of the seed polysilicon is preferably 540xc2x0xcx9c670xc2x0 C., more preferably 570xc2x0xcx9c650xc2x0 C. Below 540xc2x0 C., the inconvenience in incurred that the reaction is slow, while in contrast, when above 670xc2x0 C., the inconvenience is incurred that the crystal particles become too large.
The pressure during the growth of the seed polysilicon layer is preferably 10 Psxcx9catmospheric pressure, and more preferably 30 Paxcx9catmospheric pressure. Below 10 Ps, the inconvenience is incurred that the growth is slow, while when above atmospheric pressure, the distribution of the thickness deteriorates.
The thickness of the seed polysilicon layer is preferably 50xcx9c5000 nm, and more preferably 100xcx9c3000 nm. Below 50 nm, there is the concern that when laminating the high temperature polysilicon surface, due to the etching action of the polysilicon, parts of this seed polysilicon layer are dissipated, and holes may be produced. Above 5000 nm, the inconvenience is incurred that it becomes unnecessarily thick.
For the anisotropic etchant, it is possible to use alkaline etchants such as KOH (IPA/KOH/H2O), KOH (KOHH2O), KOH (hydrazine/KOH/H2O). The normal conditions for anisotropic etching can be adopted.
In addition, it is possible to use generally adopted conditions for each step in forming the windows of the isotropic etching on the negative resist film on the surface of the wafer.
According to this invention, a relatively thin seed polysilicon layer is grown on the surface of a dielectrically separating oxide film by the low temperature CVD method, and subsequently, a polysilicon layer is grown on the surface of this seed polysilicon layer by the high temperature CVD method.
The particle diameter of the crystals is smaller when the polysilicon is grown by the low temperature CVD method compared to the growth by the high temperature CVD method. As a result, even if there are particles or defects on the surface of the dielectrically separating oxide film, these will gradually be covered by the seed polysilicon, which has good coating characteristics. Therefore, the smoothness of the surface of the seed polysilicon layer is increased.
Thus, subsequently, when polysilicon is grown by the high temperature CVD method on this very flat surface, a growth occurs that is different from the growth of large polysilicon cores of the conventional means. That is, over the entire surface of this dielectrically separating oxide film, the polysilicon grows at an approximately uniform thickness. Thereby, it is possible to decrease the voids that develop between the dielectrically separating oxide film and the polysilicon layer.
Thereby, it is possible to eliminate concavities in the polysilicon layer surface exposed on the dielectrically separated wafer surface and the voids, and to eliminate gaps from the interface between the polysilicon layer and the dielectrically separating oxide film in the dielectrically separated wafer.
An object of the third embodiment of the present invention is solve the third problems by providing a dielectrically separated wafer and a fabrication method for the same that can flatten the surface between dielectrically separated silicon islands of a dielectrically separated wafer.
The third embodiment provides a dielectrically separated wafer and a fabrication method for the same that allows simultaneous implementation of the realization of dielectrically separated silicon islands having a comparably large surface area relative to the wafer surface, the prevention of damage to the mask in the contact exposure process, the prevention of contaminants adhering between dielectrically separated silicon islands, the realization of uniform application of the resist to the wafer surface, and prevention of resist film form remaining of the wafer surface.
A first aspect of the third embodiment of the present invention is a dielectrically separated wafer having a plurality of dielectrically separated silicon islands insulated by a dielectrically separating oxide film on the wafer surface, wherein the surface between one dielectrically separated silicon island and another neighboring dielectrically separated silicon island is formed so as to be flat.
Normally, the dielectrically separated silicon island is formed using a polysilicon layer as a base. This polysilicon layer is formed by the CVD method. In the CVD method, a source gas (material gas) including silicon is introduced into a reaction furnace along with a diluting gas (normally, N2 gas), and silicon generated by thermal decomposition or reduction of the material gas is deposited on a silicon wafer heated to a high temperature. Compounds that incorporate silicon include, for example, trichlorosilane (SiHCl3), silicon tetrachloride (SiCl4), as well as, for example, monosilane (SiH4) and dichlorosilane (SiH2Cl2). In addition, the CVD method includes, for example, the high temperature CVD method at 1200xcx9c1300xc2x0 C. and the low temperature CVD method at 550xcx9c700xc2x0 C.
Reaction furnaces include, for example, the pancake shaped furnace that induction heats a silicon wafer on a boat fixed in a lateral quartz tube while gas is being feed. In addition, there is the vertical shaped furnace that resistance heats a vertical quarts (SiC) boat upon which the silicon wafer is placed while rotating it and feeding gas.
Here, the flattening of the surface between the dielectrically separated silicon islands means that, when using a stylus-type step measurer, the absolute value of the difference between the largest measured value and the smallest measured value is less than 0.2 xcexcm. However, if the amount of polishing of the surface of the dielectrically separated wafer can flatten the wafer surface between dielectrically separated silicon islands, it is not particularly limited. Moreover, the amount of polishing necessary for this flattening differs depending on such polishing conditions as the corrosion resistance of the polysilicon layer and the thickness of the dielectrically separating insulating film.
A second aspect of the third embodiment is a dielectrically separated silicon wafer for which the flatness of the surface between these dielectrically separated silicon islands is less than 0.2 xcexcm, which is the absolute value of the difference between the maximum value and the minimum value when this surface is measured by a stylus-profilometer.
When the absolute value of the difference exceeds 0.2 xcexcm, such inconveniences are incurred as unevenness of the surface, damage to the mask during contact exposure, resist adhesion, blurred resolution, resist remaining, and contamination. This falls under a fourth aspect of the present invention.
A third aspect of the third embodiment is a fabrication method for a dielectrically separated wafer including the steps of forming dielectrically separating grooves by anisotropic etching on the silicon wafer surface, coating a dielectrically separating insulating film on the surface of a silicon wafer including these dielectrically separating grooves, depositing a polysilicon layer by the high temperature CVD method on this dielectrically separating insulating film, and providing a plurality of dielectrically separated silicon islands insulated by a dielectrically separating insulating film by separation polishing the silicon surface of the side of the silicon wafer opposite to the side on which the polysilicon layer is deposited, and wherein depending on the corrosion resistance of this deposited polysilicon layer, the thickness of this dielectrically separating insulating film, the etching depth for forming these dielectrically separating grooves, and the distance between neighboring dielectrically separated silicon islands, the surface between one dielectrically separated silicon island and a neighboring dielectrically separated silicon island is flattened by changing the conditions of the separation polishing of the silicon surface.
Here, the corrosive resistance of the polysilicon layer relates to the type of source gas, the distinction between high temperature CVD method and low temperature CVD method, and the particle diameter and speed of growth of this polysilicon layer.
In addition, the thickness of the dielectrically separating insulating film is determined by the required pressure resistance of the devices. The typical thickness is 0.7xcx9c3.0 xcexcm. Under 0.7 xcexcm, it meets few requirements as a high pressure resistant substrate. In addition, when exceeding 3.0 xcexcm, the problems of worsening fabrication characteristics and serious warping are incurred. In addition, dislocated pits are easily produced.
Furthermore, the etching depth for forming the dielectrically separating grooves is determined depending on pressure resistance requirements of the elements to be produced, and for light elements, the attenuation depth of the light. This depth would be, for example, 10xcx9c70 xcexcm.
The distance between neighboring dielectrically separated silicon islands is determined by the chip size and requirements of the circuit structure, along with the precision of the processing, and is, for example, 0xcx9c40 xcexcm. The 0 xcexcm distance is the case that the silicon islands are only insulted from each other by a separation oxide film.
Examples of the conditions for the separation polishing of the silicon surface are the conditions of the abrasive used to polish the surface of the dielectrically separated wafer. As an abrasive, it is possible to use, for example, an alkaline etchant adding to 2xcx9c5wt. % an abrasive grain with average particle diameters of about 20xcx9c100 nm. Preferably, the abrasive has a pH of 9xcx9c11.
As a method for forming the polysilicon layer, for example, the reduced pressure CVD method and the atmospheric pressure CVD method are used. The pressure while growing the film by the reduced pressure CVD method is about 10xcx9c80 Pa.
A fourth aspect of the third embodiment is a dielectrically separated wafer whose surface smoothness between dielectrically separated silicon islands is less than 0.2 xcexcm, which is the absolute value of the difference between the maximum value and the minimum value when this surface is measured by a stylus-profilometer.
According to this invention, the surface of the dielectrically separated wafer is polished only to the degree necessary to become a smooth surface without protrusions or indentations between one dielectrically separated island and another dielectrically separated island.
As a result, it is possible to realize dielectrically separated islands that have a relatively large surface area with respect to the wafer surface area. Furthermore, at the same time, this allows preventing damage to the resist film during the contact exposure process in device fabrication, preventing contamination from adhering between the dielectrically insulated islands, realizing a uniformly applied resist film on the wafer surface, and the prevention of this film from remaining on the wafer surface during the resist film stripping.
In particular, in the second and fourth aspects of the invention, the smoothness of the surface between dielectrically separated silicon islands is less than 0.2 xcexcm, which is the absolute value of the difference between the maximum value and the minimum value when measured by a stylus-profilometer.
In addition, in the third aspect of the invention, the conditions of the separation polishing of the silicon surface and the flattening of the surface between the dielectrically separated islands depend on the corrosion resistance of the polysilicon layer, thickness of the dielectrically separating insulating film, the depth of etching, and the distance between neighboring dielectrically separated silicon islands.